1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device with a bonding pad structure.
2. Description of the Related Art
As electrical components are made smaller, various strategies have been adopted to reduce the amount of space devoted to connections between the chips containing the integrated circuit devices and the printed circuit board on which the chips are mounted. Electrical connections between integrated circuits on a chip and the printed circuit board are made through bonding pads typically provided at the periphery of the chip.
Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads are required to transmit power, ground and input/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a high per chip yield.
Conventional bonding pad structures have been observed to delaminate or have layers that separate from one another in response to external forces like those applied in wire bonding processes of the type typically used attaching wires to the bonding pads.
The general bonding pad structure consists of metal layers, emanating from the terminals of the chip devices, separated by intermetal dielectric (IMD) layers that are often silicon oxide. Metal vias, tungsten (W) often being used, pass through the IMD layers connecting the metal layers. Wires are bonded to a bonding metal pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
One mode of failure of the bonding pad relates to the peeling of the wire from the metal pattern due to forces exerted especially during the bonding process. A bonding pad structure with increased peeling resistance and a cleaning method to ensure contamination free bonding have been disclosed in the prior art. Besides, another failure mode that has been observed relates to bonding pad peel back, where forces during wire bonding may cause a delaminating of one or more of the underlying layers. Bonding pad structures that resist bonding pad peeling have been also recited in the related filed.
It has been observed that wire bonding may cause the bonding pad to lift off or peel back (delaminate) from one or more of the underlying layers, weakening the bonding pad structure and damaging other portions of the chip's wiring. Such peel back reduces or prevents electrical contact between the bonding pad and the integrated circuit devices on the chip, which decreases the reliability and reduces the life of the chip.
Once a small crack is initiated it will, under stresses prevalent in the layer during processing, grow extensively. Approaches to alleviate this cracking of the IMD focus on producing IMD layers with low residual stress. Composite silicon oxide layers serve this purpose and are used, such as HDP plus PETEOS layers. However, even with composite silicon oxide layers to reduce stress, the IMD layer is not strong enough to withstand stresses encountered during chip packaging and IMD cracking is still observed.
It is desirable to form bonding pad structures exhibiting improved durability with better adhesion to underlying layers, so that the bonding pad structures are more compatible with chip-on-board techniques.